Semiconductors are used in integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. One type of semiconductor device is a semiconductor storage device, such as a dynamic random access memory (DRAM) and flash memory, which uses a charge to store information.
Various memory types are in common use to store digitally a substantial amount of data. DRAMs have moderate cost, are very fast and can have access times on the order of about 30 nanoseconds, but lose the stored data upon loss of electrical power, i.e., they are “volatile”. “Flash” memories are non-volatile, and the time required to store the first information in the memory is long (ms-s). Hard-disk drives are substantially lower in cost than DRAMs, are non-volatile, but have access times generally greater than a millisecond. Further application considerations for each technology include limitations on the number of times a memory cell can be written or read before it deteriorates, how long it reliably retains data, its data storage density, how much energy it consumes, the need for integral mechanical devices such as for disk drives and tapes, and the complexity and expense of associated circuitry. Considering these limitations, there is now no ideal technology for general applications. Magnetic random access memory (MRAM) as described below appears to have properties that position it well for widely accepted digital memory applications, overcoming many of these limitations.
Spin electronics, which combines semiconductor technology and magnetics, i.e., which utilizes both the discrete electron charge and magnetic moment of electrons, is a relatively recent development in semiconductor memory devices. The spin of an electron, rather than the charge, is used to indicate the presence of a logic “1” or “0”. One such spin electronic device is a resistive memory device referred to as a magnetic random access memory, which includes conductive lines usually positioned perpendicular to one another in different metal layers, the conductive lines sandwiching a magnetic stack which functions as a memory cell. The place where the conductive lines intersect is called a cross-point. A current flowing through one of the conductive lines generates a magnetic field around the conductive line and orients the magnetic polarity of one layer of the magnetic stack. A current flowing through the other conductive line induces a superimposed magnetic field and can partially turn the magnetic polarity, also. Digital information, represented as a “0” or “1”, is storable in the alignment of magnetic moments in the magnetic stack. The resistance of the magnetic stack depends on the moment's alignment. The stored state is read from the magnetic stack by detecting the component's resistive state. An array of memory cells may be constructed by placing the conductive lines in a matrix structure having rows and columns, with the magnetic stack being placed at the intersection of the conductive lines.
A key advantage of MRAMs compared to traditional semiconductor memory devices, such as DRAMs, is that MRAMs are non-volatile upon removal of electrical power. This is advantageous because a personal computer (PC) utilizing MRAMs could be designed without a long “boot-up” time as with conventional PCs that utilize DRAMs, as an example. Moreover, MRAMs do not need to be rewritten when they are read. In addition, MRAMs have the potential for read/write speeds in the range of a few nanoseconds, which compares favorably with fast memory technologies now available.
Another application of magnetic tunnel junction cell cells is for galvanic decouplers (also called galvanic isolators). Galvanic decouplers are used in applications where dielectric isolation, i.e., the absence of a metallic connection, is required between two circuits that require a signal to be communicated from one to the other. When the signal to be communicated is digital, opto-isolators are frequently used, which are generally configured with a light-emitting diode transmitter and a diode (or transistor) receiver, separated by an intervening insulating medium. Opto-isolators are often limited in performance by a maximum data rate due in part to their ability to transmit one bit of data at a time. When substantial data must be communicated quickly, multiple opto-isolators are often required, which can consume valuable circuit-board space.
FIG. 1 illustrates a magnetic tunnel junction (MTJ) stack capable of registering (or storing, or being programmed with) one bit that comprises a resistive or magnetic memory cell. The terms “memory cell,” “MTJ,” “MTJ cell,” and “MTJ stack” are used interchangeably herein and refer to the MTJ shown in FIG. 1. The MTJ comprises at least two ferromagnetic layers M1 and M2 that are separated by a tunnel layer TL. The MTJ stack is positioned at the cross-point of two conductors, referred to as a wordline WL and a bitline BL. One magnetic layer M1 is referred to as a free layer or a storage layer, and the other magnetic layer M2 is referred to as a fixed layer or a reference layer. Two publications describing the art of MRAMs are S. Tehrani, et al., “Recent Developments in Magnetic Tunnel Junction MRAM,” IEEE Trans. on Magnetics, Vol. 36 Issue 5, September 2000, pp. 2752–2757, and J. DeBrosse, A. Bette et al., “A High Speed 128-kb MRAM Core for Future Universal Memory Applications,” IEEE Journal of Solid State Circuits, Vol. 39, Issue 4, April 2004, pp. 678–683. The magnetic orientation of the free layer M1 can be changed by the superposition of the magnetic fields caused by a programming current IBL that is run through the bitline BL and a programming current IWL that is run through the wordline WL. A bit, e.g., a “0” or “1”, may be stored (or “programmed”) in the MTJ stack by changing the orientation of the field of the free magnetic layer relative to that of the fixed magnetic layer. If both magnetic layers M1 and M2 have the same orientation, the MTJ stack has a lower resistance RC. The resistance RC is higher if the magnetic layers have opposite magnetic orientations.
A free layer may be formed as a soft ferromagnetic layer or, alternatively, may be configured as a stack of more than one ferromagnetic layer, each ferromagnetic layer separated by an antiferromagnetic coupling spacer layer. Such an arrangement is referred to as a synthetic antiferromagnetic layer and is described in the publication M. Durlam, et al., A 0. 18 um 4 Mb Toggling MRAM, EDM 2003. In this publication, the alternative to configure the free layer as a synthetic antiferromagnetic layer is described.
FIG. 2 illustrates an MTJ configured as a memory cell of an MRAM device 10 from an array of MRAM devices, having a select transistor X1. In some MRAM array designs, the MTJ stack is combined with a select transistor X1, as shown in FIG. 2, which is a cross-sectional view of a 1T1MTJ design (one transistor and one MTJ. stack). The 1T1MTJ design uses the select transistor X1 for fast access of the MTJ during a read operation. A schematic diagram of the MTJ stack and select transistor X1 is shown in FIG. 3. A bitline BL is coupled to one side of the MTJ stack, and the other side of the MTJ stack is coupled to the drain D of the select transistor X1 by metal layer MX, via VX, and a plurality of other metal and via layers, as shown. The source S of the transistor X1 is coupled to ground (GND). X1 may comprise two parallel transistors that function as one transistor, as shown in FIG. 2. Alternatively, X1 may comprise a single transistor, for example. The gate G of the transistor X1 is coupled to a read wordline (RWL), shown in phantom, that is preferably positioned in a different direction than, e.g., perpendicular to, the bitline BL direction.
The select transistor X1 is used to access the memory cell's MTJ. In a read (RD) operation during current sensing, a constant voltage is applied at the bitline BL. The select transistor X1 is switched on, e.g., by applying a voltage to the gate G by the read wordline RWL, and current then flows through the bitline BL, the magnetic tunnel junction MTJ, over the MX layer, down the metal and via stack, through the transistor drain D, and through the transistor X1 to ground GND. This current is then measured and is used to determine the resistance of the MTJ, thus determining the programming state of the MTJ. To read another cell in the array, the transistor X1 is switched off, and the select transistor of the other cell is switched on.
The programming or write operation is accomplished by programming the MTJ at the cross-points of the bitline BL and the programming line or write wordline WWL using selective programming currents. For example, a first programming current IBL passed through the bitline BL causes a first magnetic field component in the MTJ stack. A second magnetic field component is created by a second programming current IWL that is passed through the write wordline WWL, which may run in the same direction as the read wordline RWL of the memory cell, for example. The superposition of the two magnetic fields at the MTJ produced by programming currents IBL and IWL causes the MTJ stack to be programmed. To program a particular memory cell in an array, typically a programming current is run through the write wordline WWL, which creates a magnetic field at all cells along that particular write wordline WWL. Then, a current is run through one of the bitlines, and the superimposed magnetic fields switch only the MTJ stack at the cross-point of the write wordline WWL and the selected bitline BL.
Current sensing may be used to detect a resistance change of resistive memory cells. Current sensing is the desired method of sensing the state of MRAM cells, for example. In current sensing, a voltage is applied to the bitline, and the bitline voltage is kept constant with a sense amplifier. The cell current is directly measured, with the cell current being dependent on the resistance of the memory cell being read. The use of current sensing reduces the capacitive load problem from long bitlines that may occur in voltage sensing because the voltage of the sensed lines is held constant, thereby avoiding altering charge in the different interconnection capacitances of different memory cells.
However, a limitation of a magnetic tunnel junction cell as described above is its ability to be programmed with only a single bit of information, a limitation shared with memory elements that are based on charge storage such as a DRAM or on switching transistor pairs such as in a static RAM (SRAM). This one-bit limitation of magnetic tunnel junction cells arises from the two stable magnetic orientations of its free magnetic layer, whereby one orientation is utilized to represent a “0”, and the other, a “1”. The origin of this limitation is the variation of magnetic energy associated with the magnetic tunnel junction cell depending on the orientation of the direction of the free magnetic layer. Magnetic energy minima for the field orientation of the free magnetic layer occur in two directions that are substantially 180 degrees apart, with energy maxima at 90 and 270 degrees. The “0” and “1” memory states utilize the two energy minima for the data storage. The energy maxima represent unstable states, and the energy difference between a stable state and an intervening unstable state is a measure of data storage reliability, i.e., of the resistance to data loss caused by the random, thermal energy (“Boltzmann energy”) of the freely orientable magnetic layer that is proportional (via Boltzmann's constant) to the absolute temperature of the device.
To achieve a high storage density, an alternative to storing multiple bits of information per cell is to decrease the feature sizes of the cells so as to increase the physical cell density. However, the activation energy of a cell varies as the cell volume, and consequently, with a small energy barrier inherently associated with small cells, random loss of data can occur in cells that are too small due to the stochastic processes associated with ordinary thermal effects. A memory design for a substantial quantity data that can reliably retain every bit for 10 years or more without thermally induced random data loss preferably requires an energy barrier between stable states of at least 200 kBT (or about 5 eV at room temperature) where kB is Boltzmann's constant and T is the absolute operating temperature of the device.
Thus, to be programmed with more than one bit in a single memory cell a technique is required for creating more than two energy minima associated with the magnetization direction of the free magnetic layer so that more than one bit of information can be programmed in a single magnetic tunnel junction cell. To program two bits in one cell, at least four energy minima are required coupled with a process for enabling a transition from any energy minimum to any other energy minimum so that the two bits to be programmed can be freely chosen. Sufficiently high intervening energy maxima, i.e., sufficient activation energies, are required to preserve the data reliability, which generally requires significant anisotropy for the free magnetic layer.
The devices described herein with a resistance dependent on a programmed state of a free magnetic layer are preferably based on the tunneling magnetoresistance effect (TMR), but, alternatively, may be based on other magnetic-orientation dependent resistance effects such as the giant magnetoresistance effect (GMR) or other magnetic-orientation dependent resistance effects relying on the electron charge and its magnetic moment. The programmable resistance devices described herein will generally be described as TMR devices with a resistance dependent on its programmed magnetic state, but other devices based on the GMR or other effects wherein a resistance is dependent on its magnetically programmed state may be readily substituted for the TMR devices within the broad scope of the present invention.